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Datasheet

Electrical Specifications

2.3.1

VCC Decoupling

Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)

and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the

large current swings when the part is powering on, or entering/exiting low power states, must be

provided by the voltage regulator solution (VR). For more details on this topic, refer to the

applicable VRD design guide.

2.3.2

FSB GTL+ Decoupling

The Celeron D processor integrates signal termination on the die as well as incorporating high

frequency decoupling capacitance on the processor package. Decoupling must also be provided by

the system baseboard for proper GTL+ bus operation.

2.3.3

FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor.

As in previous generation processors, the Celeron D processor core frequency is a multiple of the

BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during

manufacturing.

The Celeron D processor uses a differential clocking implementation. For more information on the

Celeron D processor clocking, refer to the CK409 Clock Synthesizer/Driver Specification or

CK408 Clock Synthesizer/Driver Specifications.

Table 2-1. Core Frequency to FSB Multiplier Configuration

Multiplication of System Core

Frequency to FSB Frequency

Processor

Number

Core Frequency

(133 MHz BCLK/

533 MHz FSB)

Notes1

NOTES:

Individual processors operate only at or below the rated frequency.

1/24

350

3.20 GHz

—

1/23

345

3.06 GHz

—

1/22

340

2.93 GHz

—

1/21

335

2.80 GHz

—

1/20

330

2.66 GHz

—

1/19

325

2.53 GHz

—

1/18

320

2.40 GHz

—

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