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KM4132G271B Folha de dados(PDF) 23 Page - Samsung semiconductor |
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KM4132G271B Folha de dados(HTML) 23 Page - Samsung semiconductor |
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23 / 51 page ![]() KM4132G271B CMOS SGRAM - 23 Rev. 2.4 (May 1998) 1. tRDL : 1 CLK, Last Data in to Row Precharge. 2. tBDL : 1 CLK, Last Data in to Burst Stop Delay. 3. Number of valid output data after Row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely. 4. PRE : Both banks precharge if necessary. MRS can be issued only at all bank precharge state. 8. Burst Stop & Precharge Interrupt D0 D1 D2 CLK CMD DQ WR PRE D3 1) Write Interrupted by Precharge (BL=4) tRDL Note 1 3) Read Interrupted by Precharge (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD PRE Q0 Q1 Q0 Q1 1 2 Note 3 9. MRS & SMRS CLK SMRS 2) Special Mode Register Set D0 D1 D2 CLK CMD DQ WR STOP 2) Write Burst Stop (Full Page Only) 4) Read Burst Stop (Full Page Only) CLK CMD DQ(CL2) DQ(CL3) RD STOP Q0 Q1 Q0 Q1 1 2 Note 3 BW 1CLK CMD DQM tBDL *Note : CLK PRE 1) Mode Register Set MRS ACT Note 4 tRP 1CLK CMD ACT SMRS SMRS 1CLK 1CLK 1CLK |
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