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KM4132G271B Folha de dados(PDF) 47 Page - Samsung semiconductor |
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KM4132G271B Folha de dados(HTML) 47 Page - Samsung semiconductor |
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47 / 51 page ![]() KM4132G271B CMOS SGRAM - 47 Rev. 2.4 (May 1998) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Mode Register Set Cycle HIGH Auto Refresh *Note : 1. CS, RAS, CAS, & WE activation and DSF of low at the same clock cycle with address key will set internal mode register. 2. Minimum 1 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. New Command New Command Hi-Z Hi-Z tRC HIGH MODE REGISTER SET CYCLE * Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. Auto Refresh Cycle DQ ADDR CAS RAS CS CKE CLOCK WE DQM Key Ra *Note 3 *Note 1 *Note 2 ¡ó ¡ó ¡ó ¡ó ¡ó ¡ó ¡ó ¡ó ¡ó ¡ó ¡ó ¡ó ¡ó ¡ó ¡ó DSF ¡ó ¡ó MRS : Don ′t care |
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