ADS62C17_1 datasheet(21/67 Pages) TI

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ADS62C17

www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

A7 – A0 IN HEX

Output clock edge control

LVDS Interface

D7-D5

<CLKOUT POSN> Output clock rising edge position

000, 100 Default output clock position (refer to timing specification table)

101 Rising edge shifted by + (4/26)Ts

110 Rising edge aligned with data transition

111 Rising edge shifted by – (4/26)Ts

D4-D2

<CLKOUT POSN> Output clock falling edge position

000, 100 Default output clock position (refer to timing specification table)

101 Falling edge shifted by + (4/26)Ts

110 Falling edge aligned with data transition

111 Falling edge shifted by – (4/26)Ts

CMOS INterface

D7-D5

<CLKOUT POSN> Output clock rising edge position

000, 100 Default output clock position (refer to timing specification table)

101 Rising edge shifted by + (4/26)Ts

110 Rising edge shifted by – (6/26)Ts

111 Rising edge shifted by – (4/26)Ts

D4-D2

<CLKOUT POSN> Output clock falling edge position

000, 100 Default output clock position (refer to timing specification table)

101 Falling edge shifted by + (4/26)Ts

110 Falling edge shifted by – (6/26)Ts

111 Falling edge shifted by – (4/26)Ts

A7 – A0 IN HEX

<ENABLE INDEPENDENT

CHANNEL CONTROL>

2s complement or offset binary 0

0 Common control – both channels use common control settings for test patterns, offset correction,

gain, gain correction and SNRBoost functions. These settings can be specified in a single set of

registers.

1 Independent control – both channels can be programmed with independent control settings for test

patterns, offset correction and SNRBoost functions. Separate registers are available for each

channel.

D2-D1

10 2s complement

11 Offset binary

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