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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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ADS62C17 Folha de dados(PDF) 1 Page - Texas Instruments |
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ADS62C17 Folha de dados(HTML) 1 Page - Texas Instruments |
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1 / 67 page  1 FEATURES DESCRIPTION ADS62C17 www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009 Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost • Programmable Gain up to 6dB for SNR/SFDR Trade-off • Maximum Sample Rate: 200 MSPS • DC Offset Correction • 11-bit Resolution with No Missing Codes • Gain Tuning Capability in Fine Steps (0.001 • 90 dBc SFDR at Fin = 10 MHz dB) Allows Channel-to-channel Gain Matching • 79.8 dBFS SNR at 125 MHz IF, 20 MHz BW • Supports Input Clock Amplitude Down to 400 using TI proprietary SNRBoost technology mV p-p Differential • Total Power 1.1 W at 200 MSPS • Internal and External Reference Support • 90 dB Cross-talk • 64-QFN Package (9 mm × 9 mm) • Double Data Rate (DDR) LVDS and Parallel CMOS Output Options ADS62C17 is a dual channel 11-bit, 200 MSPS A/D converter that combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications. ADS62C17 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation due to quantization noise for bandwidths less than Nyquist (Fs/2). It includes several useful and commonly used digital functions such as ADC offset correction, gain (0 to 6 dB in steps of 0.5 dB) and gain tuning (in fine steps of 0.001 dB). The gain option can be used to improve SFDR performance at lower full-scale input ranges. Using the gain tuning capability, each channel’s gain can be set independently to improve channel-to-channel gain matching. The device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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Descrição semelhante - ADS62C17_1 |
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