ADS62C17_1 datasheet(5/67 Pages) TI

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ELECTRICAL CHARACTERISTICS

(1)

ADS62C17

www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009

Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 200 MSPS, 50% clock duty cycle, –1dBFS

differential analog input, internal reference mode, LVDS and CMOS interfaces unless otherwise noted.

Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

bits

ANALOG INPUTS

Differential input voltage range

2.0

VPP

Differential input resistance (at dc)

See Figure 44

> 1

Ω

Differential input capacitance

See Figure 45

3.5

Analog input bandwidth

700

MHz

Analog input common mode current (per channel)

3.6

µA/MSPS

VCM common mode voltage output

1.5

VCM output current capability

±4

POWER SUPPLY

IAVDD

Analog supply current

262

IDRVDD

Output buffer supply current LVDS interface

With 100

Ω external

120

termination

IDRVDD

Output buffer supply current CMOS interface

No external load

capacitance

Analog power

865

1025

Digital power LVDS interface

216

306

Global power down

No missing codes

Assured

DC ACCURACY

DNL

Differential Non-Linearity

Fin = 170 MHz

-0.6

±0.2

0.6

LSB

INL

Integral Non-Linearity

Fin = 170 MHz

-2.5

±0.75

2.5

LSB

Offset Error

-20

±2

Offset error temperature coefficient

0.02

mV/C

Offset error variation with supply

0.5

mV/V

There are two sources of gain error – internal reference inaccuracy and channel gain error

Gain error due to internal reference inaccuracy alone

-1

±0.2

% FS

Gain error of channel alone(2)

-1

+0.2

% FS

Channel gain error temperature coefficient

0.002

Δ%/°C

Difference in gain errors

between two channels

-2

within the same device

Gain matching(3)

% FS

Difference in gain errors

between two channels

-4

across two devices

(1)

In CMOS interface, the DRVDD current scales with the sampling frequency and the load capacitance on output pins.

(2)

This is specified by design and characterization; it is not tested in production.

(3)

For two channels within the same device, only the channel gain error matters, as the reference is common for both channels.

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