UJA1075TWSLASH5V0SLASHWD datasheet(11/53 Pages) NXP

Nome de Peças	UJA1075TW/5V0/WD

Descrição Electrónicos	High-speed CAN/LIN core system basis chip

PDF	53 Pages

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Fabricante Electrônico	NXP [NXP Semiconductors]

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UJA1075_2

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Product data sheet

Rev. 02 — 27 May 2010

11 of 53

NXP Semiconductors

UJA1075

High-speed CAN/LIN core system basis chip

6.2.2 Register map

The first three bits (A2, A1 and A0) of the message header define the register address.

The fourth bit (RO) defines the selected register as read/write or read only.

Fig 4.

SPI timing protocol

SCS

SCK

sampled

floating

mce634

MSB

LSB

MSB

LSB

SDI

SDO

Table 3.

Address bits 15, 14 and 13

Write access bit 12 = 0

Read/Write access bits 11... 0

000

0 = read/write, 1 = read only

WD_and_Status register

001

0 = read/write, 1 = read only

Mode_Control register

010

0 = read/write, 1 = read only

Int_Control register

011

0 = read/write, 1 = read only

Int_Status register

UJA1075TW/5V0/WD Folha de dados(PDF) 11 Page - NXP Semiconductors