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UJA1075TW/5V0/WD Folha de dados(PDF) 15 Page - NXP Semiconductors |
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UJA1075TW/5V0/WD Folha de dados(HTML) 15 Page - NXP Semiconductors |
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15 / 53 page ![]() UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 27 May 2010 15 of 53 NXP Semiconductors UJA1075 High-speed CAN/LIN core system basis chip 2 RTHC R/W 0 reset threshold control 0: The reset threshold is set to the 90 % V1 undervoltage detection voltage (Vuvd; see Table 10) 1: The reset threshold is set to the 70 % V1 undervoltage detection voltage (Vuvd; see Table 10) 1 WSE1 R/W 0 WAKE1 sample enable 0: sampling continuously 1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled by WBC) 0 WSE2 R/W 0 WAKE2 sample enable 0: sampling continuously 1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled by WBC) Table 6. Int_Control register Bit Symbol Access Power-on default Description |
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