P89LPC9103 datasheet(45/61 Pages) NXP

45 / 61 page

P89LPC9102_9103_9107_3

Product data sheet

Rev. 03 — 10 July 2007

45 of 61

NXP Semiconductors

P89LPC9102/9103/9107

8-bit microcontrollers with two-clock accelerated 80C51 core

9.4.5 Dual channel, continuous conversion mode

This is a variation of the auto scan continuous conversion mode where conversion occurs

on two user-selectable inputs. The result of the conversion of the ﬁrst channel is placed in

result register, AD1DAT0. The result of the conversion of the second channel is placed in

result register, AD1DAT1. The ﬁrst channel is again converted and its result stored in

AD1DAT2. The second channel is again converted and its result placed in AD1DAT3. An

interrupt is generated, if enabled, after every set of four conversions (two conversions per

channel).

9.4.6 Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any

combination of the four input channels can be selected for conversion. After each channel

is converted, an interrupt is generated, if enabled, and the A/D waits for the next start

condition. May be used with any of the start modes.

9.5 Conversion start modes

9.5.1 Timer triggered start

An A/D conversion is started by the overﬂow of Timer 0. Once a conversion has started,

additional Timer 0 triggers are ignored until the conversion has completed. The Timer

triggered start mode is available in all A/D operating modes.

9.5.2 Start immediately

Programming this mode immediately starts a conversion. This start mode is available in all

A/D operating modes.

9.6 Boundary limits interrupt

The A/D converter has both a high and low boundary limit register. After the four MSBs

have been converted, these four bits are compared with the four MSBs of the boundary

high and low registers. If the four MSBs of the conversion are outside the limit an interrupt

will be generated, if enabled. If the conversion result is within the limits, the boundary

limits will again be compared after all 8 bits have been converted. An interrupt will be

generated, if enabled, if the result is outside the boundary limits. The boundary limit may

be disabled by clearing the boundary limit interrupt enable.

9.7 DAC output to a port pin with high output impedance

The A/D converter’s DAC block can be output to a port pin. In this mode, the AD1DAT3

(written to AD1DAT3), the DAC output will appear on the channel 3 pin.

9.8 Clock divider

The A/D converter requires that its internal clock source be in the range of 500 kHz to

3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock

from 1 to 8 is provided for this purpose.

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