P89LPC9103 datasheet(29/61 Pages) NXP

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P89LPC9102_9103_9107_3

Product data sheet

Rev. 03 — 10 July 2007

29 of 61

NXP Semiconductors

P89LPC9102/9103/9107

8-bit microcontrollers with two-clock accelerated 80C51 core

frequency above 12 MHz, in some applications, an external brownout detect circuit

may be required to hold the device in reset when VDD falls below the minimum

speciﬁed operating voltage.

8.7 CCLK wake-up delay

The P89LPC9102/9103/9107 has an internal wake-up timer that delays the clock until it

stabilizes depending to the clock source used.

8.8 CCLK modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can

retain the ability to respond to events that would not exit Idle mode by executing its normal

program at a lower rate. This can also allow bypassing the oscillator start-up time in cases

where Power-down mode would otherwise be used. The value of DIVM may be changed

by the program at any time without interrupting code execution.

8.9 Low power select

If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower

the power consumption further. On any reset, CLKLP is logic 0.

8.10 Memory organization

The various P89LPC9102/9103/9107 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect

addressing, using instruction other than MOVX and MOVC. All or part of the stack

may be in this area.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and status

registers, accessible only via direct addressing.

• CODE

1 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction.

8.11 Interrupts

The P89LPC9102 supports nine interrupt sources: timers 0 and 1, brownout detect,

watchdog timer/RTC, keyboard, comparator 1, and the A/D converter.

The P89LPC9103/9107 support nine interrupt sources: timers 0 and 1, serial port Tx,

serial port Rx, combined serial port Rx/Tx, brownout detect, watchdog timer/RTC,

keyboard, comparator, and the A/D converter.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in

the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global

disable bit, EA, which disables all interrupts.

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