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33902 Folha de dados(PDF) 8 Page - Freescale Semiconductor, Inc |
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33902 Folha de dados(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 31 page ![]() Analog Integrated Circuit Device Data 8 Freescale Semiconductor 33902 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 27 V, -40°C ≤ TA ≤ 125°C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit TIMING (REF TO FIG 7) TXD Dominant State Timeout tDOUT 300 600 900 µs Bus dominant clamping detection tDOM 300 700 1000 µs Propagation loop delay TXD to RXD, recessive to dominant tLRD 60 140 210 ns Propagation delay TXD to CAN, recessive to dominant tTRD - 70 110 ns Propagation delay CAN to RXD, recessive to dominant tRRD - 45 140 ns Propagation loop delay TXD to RXD, dominant to recessive tLDR 50 120 200 ns Propagation delay TXD to CAN, dominant to recessive tTDR - 75 150 ns Propagation delay CAN to RXD, dominant to recessive tRDR - 50 140 ns Loop time TXD to RXD, Slew rate 1 (Selected by P_SPI) Rec to Dom Dom to Rec tLOOPSL1 50 - 310 ns Loop time TXD to RXD, Slew rate 2 (Selected by P_SPI) Rec to Dom Dom to Rec tLOOPSL2 50 - 310 ns STATE MACHINE TIMING External Wake-up Filter Time tWAKE - 10 - µs 3-Pulse pattern wake-up - Pulse width VDIFF = 1.15 V, Ta =-40°C VDIFF = 2.0 V, Ta =-40°C VDIFF = 1.15 V, 25°C ≤ Ta ≤ 125°C. tPWIDTH 2.5 2.0 2.0 - - - - - - µs Time to report local wake-up event tLOC WAKE- REP - 35 - µs Time to report CAN wake-up event tCAN WAKE- REP - 25 - µs Device state transition time (P_SPI versus static mode change distinction) except from Standby and Go To Sleep modes tDEV-TR 8.0 - 15 µs Transition time from Standby mode to any mode tLP-NP - 35 - µs Transition time from go to sleep to Sleep mode («Go To Sleep» command) tH - 35 - µs VIO low to Sleep mode timing tVIO- SLP - 10 - ms VDD low to CAN driver disable timing tVDD-CANOFF - 10 - ms VDD low to regulator disable timing tVDDOFF - 50 - ms PSEUDO SPI (P_SPI)TIMING P_SPI Operation frequency FREQ 0.0625 - 4.0 MHz SCLK Clock High Time tWSCLKH 0.125 - 8.0 µs SCLK Clock Low Time tWSCLKL 0.125 - 8.0 µs EN to Falling Edge of STBY tSISU 40 - - ns Falling Edge of STBY to EN tSIH 40 - - ns ERR rise Time CL = 15 pF tRSO - 25 50 ns ERR fall Time CL = 15 pF tFSO - 25 50 ns |
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