TIR2000 datasheet(34/63 Pages) TI

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3–4

Number of stop bits. Bit 2 specifies either 1, 1.5, or 2 stop bits in each transmitted character.

The number of stop bits generated is defined as in the following table. The receiver clocks

only the first stop bit, regardless of the number of stop bits selected.

Bit 2 bit specified word lengths and number of stop bits generated are as follows:

BIT 2

WORD LENGTH SPECIFIED BY

BITS 0 & 1

NUMBER OF STOP BIT

GENERATED

Any word length

5 bits

1.5

6 bits

7 bits

8 bits

Parity enable bit. When bit 3 is a 1, a parity bit is generated in data transmitted between the

last data word bit and the first stop bit. In the receiver, the parity bit is checked when bit 3

is set. When bit 3 is a 0, no parity is generated or checked.

Even parity select bit. When bit 3 is set, a logic 1 in bit 4 produces even parity and a logic

0 in bit 4 produces odd parity.

Stick-parity bit. When bits 3, 4 and 5 are a 1, the parity bit is transmitted and checked as

a logic 0. When bits 3 and 5 are a 1 and bit 4 is a 0, the parity bit is transmitted and checked

as a logic 1. When bit 5 is a 0, stick parity is disabled.

Break control bit. Bit 6 is set to a 1 to force a break condition; i.e., a condition where the serial

output (SOUT) is forced to spacing (0) state. When bit 6 is set to 0, the break condition is

disabled. Bit 6 only affects the SOUT.

Divisor-latch-access bit (DLAB). Bit 7 must be set to a 1 to access the divisor latches of the

baud rate generator or bit 5 of the FIFO control register (FCR). Bit 7 must be set to 0 to

access the receiver buffer register, the transmitter holding register, or the interrupt enable

3.7

Modem Control Register (MCR) - (read and write)

Address: 4 (Hex)

Bit Definitions:

BIT NO.

DESCRIPTION

Data terminal ready (DTR). Bit 0 controls DTR.

Request to send (RTS). Bit 1 controls RTS.

Reserved

Enable IRQ. When set to a 1, the selected IRQ channel is enabled.

Loop back mode enable. When set to 1, bit 4 enables the loop back mode, i.e., it provides a local loop-back

feature for diagnostic testing of the UART.

Flow-control enable (AFE).

Reserved

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