TIR2000 datasheet(27/63 Pages) TI

27 / 63 page

2–15

NOTES: A. When CTS is a low, the transmitter keeps sending serial data out.

B. When CTS transitions to a high before the middle of the last stop bit of the current byte, the transmitter

finishes sending the current byte but it does not send the next byte.

C. When CTS transitions from a high to a low, the transmitter begins sending data again.

Start

Bits 0–7

Stop

Start

Bits 0–7 Stop

Start

Bits 0–7

Stop

SOUT

CTS

Figure 2–5. CTS Functional Timing Diagram

2.1.6.4

Enabling Auto-RTS and Auto-CTS

The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes for the 16-byte mode and 1, 16, 32, or 56

bytes for the 64-byte mode.

NOTES: A. N = receiver FIFO trigger level

B. The two blocks in dashed lines cover the case when an additional byte is sent as described in auto-CTS.

Start

Byte N

Stop

Start

Byte N + 1 Stop

Start

Byte

Stop

SIN

RTS

N + 1

Figure 2–6. RTS Functional Timing, RCV-FIFO Trigger

2.1.6.4.1

Programming UART Related Registers

All UART related registers must be programmed for proper data communication. The following register

programming steps are required for data communication:

Program the interrupt configuration register (ICR) in order to:

•

Select the IRQ channel.

•

Select either totem-pole or open-drain output.

•

Select an active high or an active low for an interrupt when the totem-pole configuration is

selected.

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