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TIR2000 Folha de dados(PDF) 21 Page - Texas Instruments

Nome de Peças TIR2000
Descrição Electrónicos  High-Speed Serial Infrared Controller With 64-Byte FIFO
PDF  63 Pages
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
Logo TI - Texas Instruments

TIR2000 Folha de dados(HTML) 21 Page - Texas Instruments

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2–9
4.
Program the IRCFG[3] bit to select fixed 1.6
µs or 3/16th pulse width
5.
Write a 1 to the ACREG[7] bit to enable data transmission.
6.
Write a 1 to the MCR[3] bit to enable the selected IRQ channel
2.1.3.2
SIR Data Receive Mode
The following register programming steps are required to receive data in SIR mode:
1.
Reset the RX FIFO. This includes:
•
Write the LCR register to set the LCR[7] bit to a 1. The LCR[7] bit must be a 1 in order to be
able to write to the FCR(5) bit.
•
Program the FCR to select 64-/16-bytes RX FIFO register, non-DMA mode of operation,
select the RX FIFO trigger level and to clear the RX FIFO.
•
Write the LCR register so that the LCR[7] bit = 0 (for normal operation).
2.
Program the IER register to enable the receive related interrupts which include:
•
RX threshold interrupt (IER[0]) bit
•
Modem-Status interrupt enable (IER[3])
•
Disable the TX related interrupts (TX FIFO below threshold interrupt and the TX underrun
interrupt).
3.
Write a 1 to the ACREG[6] bit to enable data receive.
2.1.4
SHARP Infrared (IR) mode
The SHARP IR mode of operation is similar to the SIR mode except the modulation/demodulation of the
serial data is different. The SHARP IR mode uses amplitude shift keying (ASK) modulation/demodulation.
Data transfer can take place up to a 38.4K baud rate. In the ASK modulation, a 0 is signaled by sending a
500-kHz continuous pulse and a 1 is signaled by the absence of an IR pulse (see Figure 2–3).
10
1
0
1
No Pulse
Transmit Data
IR Output
Ir Pulse
No Pulse
Ir Pulse
Figure 2–3. SHARP Ir Encoding
The following register programming steps are required for encoding in the SHARP Ir mode:
1.
Program the ICR register
2.
Program the prescaler (PRESC) register to insure the prescaler output is approximately 1.43
MHz. The default PRESC value is used for an input clock frequency of 48 MHz.
3.
Program the auxiliary baud rate divisor lower byte (ABDL) and the auxiliary baud rate divisor
higher byte (ABDH) registers to select the desired communication baud rate for the UART mode.
The baud rate is given by:
(2)
Baud rate
+
X
IN
PRESC
Divisor
16



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