AX2000-1CS896 datasheet(47/226 Pages) ACTEL

Nome de Peças	AX2000-1CS896

Descrição Electrónicos	Axcelerator Family FPGAs

PDF	226 Pages

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Fabricante Electrônico	ACTEL [Actel Corporation]

Página de início	http://www.actel.com

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Axcelerator Family FPGAs

v2.7

2-33

Table 2-39 • 3.3V GTL+ I/O Module

Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

3.3V GTL+I/O Module Timing

tDP

Input Buffer

1.75

1.99

2.35

tPY

Output Buffer

1.01

1.15

1.36

tICLKQ

Clock-to-Q for the I/O input register

0.67

0.77

0.90

tOCLKQ

Clock-to-Q for the IO output register and the I/O

enable register

0.67

0.77

0.90

tSUD

Data Input Set-Up

0.23

0.27

0.31

tSUE

Enable Input Set-Up

0.26

0.30

0.35

tHD

Data Input Hold

0.00

tHE

Enable Input Hold

0.00

tCPWHL

Clock Pulse Width High to Low

0.43

0.48

0.57

tCPWLH

Clock Pulse Width Low to High

0.45

0.51

0.60

tWASYN

Asynchronous Pulse Width

0.43

0.48

0.57

tREASYN

Asynchronous Recovery Time

0.10

tHASYN

Asynchronous Removal Time

0.00

tCLR

Asynchronous Clear-to-Q

0.23

0.27

0.31

tPRESET

Asynchronous Preset-to-Q

0.23

0.27

0.31

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