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AX2000-1CS896 Folha de dados(PDF) 63 Page - Actel Corporation

Nome de Peças AX2000-1CS896
Descrição Electrónicos  Axcelerator Family FPGAs
PDF  226 Pages
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Fabricante Electrônico  ACTEL [Actel Corporation]
Página de início  http://www.actel.com
Logo ACTEL - Actel Corporation

AX2000-1CS896 Folha de dados(HTML) 63 Page - Actel Corporation

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Axcelerator Family FPGAs
v2.7
2-49
Buffer Module
Introduction
An additional resource inside each SuperCluster is the Buffer (B) module (Figure 1-4 on page 1-3). When a fanout
constraint is applied to a design, the synthesis tool inserts buffers as needed. The buffer module has been added to
the AX architecture to avoid logic duplication resulting from the hard fanout constraints. The router utilizes this logic
resource to save area and reduce loading and delays on medium-to-high-fanout nets.
Timing Models and Waveforms
Timing Characteristics
Figure 2-33 • Buffer Module Timing Model
Figure 2-34 • Buffer Module Waveform
Table 2-63 • Buffer Module
Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C
'–2' Speed
'–1' Speed
'Std' Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
Buffer Module Propagation Delays
tBFPD
Any input to output Y
0.12
0.14
0.16
ns
IN
OUT
OUT
GND
50%
50%
50%
50%
GND
IN
VCCA
VCCA
tBFPD
tBFPD



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