CY8CTST110
Document Number: 001-46931 Rev. *B
Page 21 of 32
Figure 8. 24 MHz Period Jitter (IMO) Timing Diagram
Figure 9. 32 kHz Period Jitter (ILO) Timing Diagram
AC General Purpose IO Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C
≤ T
A ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 20. 2.7V AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FIMO12
Internal Main Oscillator Frequency for 12 MHz
11.5
120
12.7[16, 17,
18]
MHz
Trimmed for 2.7V operation
using factory trim values. See
Figure 8 on page 12. SLIMO
mode = 1.
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35[16, 17,
18]
MHz
Trimmed for 2.7V operation
using factory trim values. See
Figure 8 on page 12. SLIMO
mode = 1.
FCPU1
CPU Frequency (2.7V Nominal)
0.093
3
3.15[16, 17]
MHz
24 MHz only for SLIMO mode =
0.
FBLK27
Digital PSoC Block Frequency (2.7V
Nominal)
0
12
12.5[16, 17,
18]
MHz
Refer to the AC digital block
specifications.
F32K1
Internal Low Speed Oscillator Frequency
8
32
96
kHz
Jitter32k
32 kHz RMS Period Jitter
–
150
200
ns
Jitter32k
32 kHz Peak-to-Peak Period Jitter
–
1400
–
TXRST
External Reset Pulse Width
10
–
–
μs
FMAX
Maximum frequency of signal on row input or
row output.
–
–
12.3
MHz
TRAMP
Supply Ramp Time
0
–
–
μs
Jitter24M1
F
24M
Jitter32k
F
32K1
Table 21. 5V and 3.3V AC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FGPIO
GPIO Operating Frequency
0
–
12
MHz
Normal Strong Mode
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
3
–
18
ns
Vdd = 4.5 to 5.25V, 10% to 90%
TFallF
Fall Time, Normal Strong Mode, Cload = 50 pF
2
–
18
ns
Vdd = 4.5 to 5.25V, 10% to 90%
TRiseS
Rise Time, Slow Strong Mode, Cload = 50 pF
7
27
–
ns
Vdd = 3 to 5.25V, 10% to 90%
TFallS
Fall Time, Slow Strong Mode, Cload = 50 pF
7
22
–
ns
Vdd = 3 to 5.25V, 10% to 90%
Notes
16. 2.4V < Vdd < 3.0V.
17. Accuracy derived from IMO with appropriate trim for Vdd range.
18. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency. for user modules
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