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H8/3021 Folha de dados(PDF) 126 Page - Renesas Technology Corp |
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H8/3021 Folha de dados(HTML) 126 Page - Renesas Technology Corp |
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126 / 712 page ![]() 5. Interrupt Controller Rev.2.00 Mar. 22, 2007 Page 102 of 684 REJ09B0352-0200 5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time External Memory On-Chip 8-Bit Bus No. Item Memory 2 States 3 States 1 Interrupt priority decision 2* 1 2* 1 2* 1 2 Maximum number of states 1 to 23 1 to 27 1 to 31* 4 until end of current instruction 3 Saving PC and CCR to stack 4 8 12* 4 4 Vector fetch 4 8 12* 4 5 Instruction prefetch* 2 4 8 12* 4 6 Internal processing* 3 4 4 4 Total 19 to 41 31 to 57 43 to 73 Notes: 1. 1 state for internal interrupts. 2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt service routine. 3. Internal processing after the interrupt is accepted and internal processing after prefetch. 4. The number of states increases if wait states are inserted in external memory access. |
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