H8SLASH3021 datasheet(45/712 Pages) RENESAS

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2. CPU

Rev.2.00 Mar. 22, 2007 Page 21 of 684

REJ09B0352-0200

General register ER7 has the function of stack pointer (SP) in addition to its general-register

function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the

stack.

Free area

Stack area

SP (ER7)

Figure 2.5 Stack

2.4.3

Control Registers

The control registers are the 24-bit program counter (PC) and the 8-bit condition code register

(CCR).

Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU

will execute. The length of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so

the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is

regarded as 0.

Condition Code Register (CCR): This 8-bit register contains internal CPU status information,

including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and

carry (C) flags.

Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted

regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.

Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the

LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask

bit. For details see section 5, Interrupt Controller.

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