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HD64F2149YV Folha de dados(PDF) 217 Page - Renesas Technology Corp

Nome de Peças HD64F2149YV
Descrição Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
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HD64F2149YV Folha de dados(HTML) 217 Page - Renesas Technology Corp

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Section 7 Data Transfer Controller
Rev. 3.00 Jan 18, 2006 page 189 of 1044
REJ09B0280-0300
7.3.8
Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 7.9 shows memory mapping for chain transfer.
Source
Source
Destination
Destination
DTC vector
address
Register information
start address
Register information
CHNE = 1
Register information
CHNE = 0
Figure 7.9 Memory Mapping in Chain Transfer
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.



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