HD64F2149YV datasheet(203/1075 Pages) RENESAS

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Section 7 Data Transfer Controller

Rev. 3.00 Jan 18, 2006 page 175 of 1044

REJ09B0280-0300

7.2.7

DTC Enable Registers (DTCER)

DTCE7

R/W

DTCE6

R/W

DTCE5

R/W

DTCE4

R/W

DTCE3

R/W

DTCE0

R/W

DTCE2

R/W

DTCE1

R/W

Bit

Initial value

Read/Write

The DTC enable registers comprise five 8-bit readable/writable registers, DTCERA to DTCERE,

with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or

disable DTC service for the corresponding interrupt sources.

The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.

Bit n—DTC Activation Enable (DTCEn)

Bit n

DTCEn

Description

DTC activation by interrupt is disabled

(Initial value)

[Clearing conditions]

• When data transfer ends with the DISEL bit set to 1

• When the specified number of transfers end

DTC activation by interrupt is enabled

[Holding condition]

When the DISEL bit is 0 and the specified number of transfers have not ended

(n = 7 to 0)

A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence

between interrupt sources and DTCE bits is shown in table 7.4, together with the vector number

generated by the interrupt controller in each case.

For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions

such as BSET and BCLR. For the initial setting only, however, when multiple activation sources

are set at one time, it is possible to disable interrupts and write after executing a dummy read on

the relevant register.

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