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HD64F2149YV Folha de dados(PDF) 192 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 192 Page - Renesas Technology Corp |
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192 / 1075 page ![]() Section 6 Bus Controller Rev. 3.00 Jan 18, 2006 page 164 of 1044 REJ09B0280-0300 T1 Address bus φ RD Bus cycle A Data bus T2 T3 T1 T2 Bus cycle B Long output floating time Data collision (a) Idle cycle not inserted T1 φ RD T2 T3 TI T1 (b) Idle cycle inserted T2 HWR, LWR HWR, LWR Address bus Data bus Bus cycle A Bus cycle B Figure 6.15 Example of Idle Cycle Operation 6.6.2 Pin States in Idle Cycle Table 6.5 shows pin states in an idle cycle. Table 6.5 Pin States in Idle Cycle Pins Pin State A23 to A0, IOS Contents of next bus cycle D15 to D0 High impedance AS High RD High HWR, LWR High |
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