HD64F2149YV datasheet(1067/1075 Pages) RENESAS

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Appendix D Pin States

Rev. 3.00 Jan 18, 2006 page 1039 of 1044

REJ09B0280-0300

Port Name

Pin Name

MCU Operating

Mode

Reset

Hardware

Standby

Mode

Software

Standby

Mode

Watch

Mode

Sleep

Mode

Sub-

sleep

Mode

Subactive

Mode

Program

Execution

State

Port 96

EXCL

Clock

output

[DDR = 1] H

[DDR = 0] T

EXCL

input

[DDR = 1]

clock

output

EXCL

input

EXCL input

Clock output/

EXCL input/

input port

2, 3 (EXPE = 1)

[DDR = 0] T

2, 3 (EXPE = 0)

2, 3 (EXPE = 1)

AS, HWR,

Ports 95 to 93

AS, HWR,

2, 3 (EXPE = 0)

kept

I/O port

Ports 92, 91

kept

I/O port

2, 3 (EXPE = 1)

2, 3 (EXPE = 0)

H/kept

Port 90

LWR

2, 3 (EXPE = 1)

LWR/

I/O port

LWR/

I/O port

2, 3 (EXPE = 0)

kept

I/O port

kept*

I/O port

Port A

A23 to A16

2, 3 (EXPE = 1)

A23 to A16/

I/O port

A23 to A16/

I/O port

2, 3 (EXPE = 0)

I/O port

T/kept

Port B

D7 to D0

2, 3 (EXPE = 1)

D7 to D0/

I/O port

D7 to D0/

I/O port

2, 3 (EXPE = 0)

kept

I/O port

kept

I/O port

Ports C to G

(H8S/2169)

2, 3 (EXPE = 1)

2, 3 (EXPE = 0)

Legend:

High

Low

High-impedance state

kept:

Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, MOS input pull-

ups remain on).

Output ports maintain their previous state.

Depending on the pins, the on-chip supporting modules may be initialized and the I/O port

function determined by DDR and DR used.

DDR: Data direction register

Note:

In the case of address output, the last address accessed is retained.

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