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HD64F2149YV Folha de dados(PDF) 1033 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 1033 Page - Renesas Technology Corp |
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1033 / 1075 page ![]() Appendix C I/O Port Block Diagrams Rev. 3.00 Jan 18, 2006 page 1005 of 1044 REJ09B0280-0300 D R QD P42DR C Reset R Q P42DDR C Reset WP4D *1 *2 WP4 SCI2 Input enable Clock output SDA1 output SDA1 input Transmit enable Output enable Clock input IIC1 8-bit timer 0 Reset input P42 RP4 Legend: WP4D WP4 RP4 : Write to P4DDR : Write to port 4 : Read port 4 Notes: 1. Output enable signal 2. Open drain control signal Hardware standby Figure C.10 Port 4 Block Diagram (Pin P42) |
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