HD64F2149YV datasheet(980/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 952 of 1044

REJ09B0280-0300

TCSR0—Timer Control/Status Register 0

H'FFA8

WDT0

OVF

R/(W)*

WT/

R/W

TME

R/W

RSTS

R/W

RST/

NMI

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

Read/Write

TCSR0

Clock select 2 to 0

CKS2

φ/2

φ/64

φ/128

φ/512

φ/2048

φ/8192

φ/32768

φ/131072

CKS1

CKS0

Note: * Only 0 can be written, to clear the flag.

Clock

Reset or NMI

NMI interrupt requested

Internal reset requested

Timer enable

TCNT is initialized to H'00 and halted

TCNT counts

Reserved bit

Timer mode select

Interval timer mode: Sends the CPU an interval timer interrupt

request (WOVI) when TCNT overflows

Watchdog timer mode: Generates a reset or NMI interrupt when

TCNT overflows

RESO pin output goes low simultaneously (when internal reset

is selected)

Overflow flag

[Clearing conditions]

• Write 0 in the TME bit

• Read TCSR when OVF = 1, then write 0 in OVF

[Setting condition]

When TCNT overflows (changes from H'FF to H'00)

(When internal reset request generation is selected in watchdog

timer mode, OVF is cleared automatically by the internal reset.)

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