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HD64F2149YV Folha de dados(PDF) 597 Page - Renesas Technology Corp

Nome de Peças HD64F2149YV
Descrição Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
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Section 17 Keyboard Buffer Controller
Rev. 3.00 Jan 18, 2006 page 569 of 1044
REJ09B0280-0300
12
3
KCLK
(pin state)
KD
(pin state)
KCLK
(input)
KCLK
(output)
KB7 to KB0
PER
KBS
KBF
Start
bit
Parity bit Stop bit
Receive processing/
error handling
Automatic I/O inhibit
Previous data
Receive data
Flag cleared
9
10
11
7
01
KB0
KB1
[1] [2] [3]
[4] [5]
[6]
Figure 17.4 Receive Timing
17.3.2
Transmit Operation
In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an
output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit,
and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit
processing flowchart is shown in figure 17.5, and the transmit timing in figure 17.6.



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