HD64F2149YV datasheet(582/1075 Pages) RENESAS

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 554 of 1044

REJ09B0280-0300

• Notes on Arbitration Lost in Master Mode

The I

2C bus interface recognizes the data in transmit/receive frame as an address when

arbitration is lost in master mode and a transition to slave receive mode is automatically

carried out.

When arbitration is lost not in the first frame but in the second frame or subsequent frame,

transmit/receive data that is not an address is compared with the value set in the SAR or SARX

2C bus interface erroneously recognizes that the address call has occurred. (See

figure 16.24.)

In multi-master mode, a bus conflict could happen. When The I

2C bus interface is operated in

master mode, check the state of the AL bit in the ICSR register every time after one frame of

data has been transmitted or received.

When arbitration is lost during transmitting the second frame or subsequent frame, take

avoidance measures.

SLA

DATA2

SLA

DATA3

DATA4

DATA1

I2C bus interface

(Master transmit mode)

Transmit data match

Transmit timing match

• Receive address is ignored

• Automatically transferred to slave

receive mode

• Receive data is recognized as

an address

• When the receive data matches to

the address set in the SAR or SARX

as a slave device

• Arbitration is lost

• The AL flag in ICSR is set to 1

Transmit data does not match

Other device

(Master transmit mode)

I2C bus interface

(Slave receive mode)

Data contention

Figure 16.24 Diagram of Erroneous Operation when Arbitration is Lost

Though it is prohibited in the normal I

2C protocol, the same problem may occur when the MST

bit is erroneously set to 1 and a transition to master mode is occurred during data transmission

or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit

when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1

according to the order below.

(a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting

the MST bit.

(b) Set the MST bit to 1.

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