HD64F2149YV datasheet(568/1075 Pages) RENESAS

568 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 540 of 1044

REJ09B0280-0300

End

Set TRS = 0 in ICCR

Set ACKB = 1 in ICSR

Set WAIT = 0 in ICMR

Read IRIC in ICCR

Clear IRIC in ICCR

Read ICDR

Clear IRIC in ICCR

Set ACKB = 0 in ICSR

Set WAIT = 1 in ICMR

Write BBSY = 0

and SCP = 0 in ICCR

Last receive ?

IRIC = 1 ?

Yes

Last receive ?

Yes

Read IRIC in ICCR

IRIC = 1 ?

Yes

Read IRIC in ICCR

IRIC = 1 ?

Yes

Set TRS = 1 in ICCR

Read ICDR

Clear IRIC in ICCR

[4]

Clear IRIC to trigger the 9th clock.

(to end the wait insertion)

[7]

Clear IRIC.

[1]

Select receive mode.

[2]

Start receiving. The first read

is a dummy read. After reading

ICDR, please clear IRIC immediately.

[3]

Wait for 1 byte to be received

(8th clock falling edge)

[9]

Clear IRIC to trigger the 9th clock.

(to end the wait insertion)

[10] Set ACKB = 1 so as to return no

acknowledge, or set TRS = 1 so as

not to issue extra clock.

[11] Clear IRIC to trigger the 9th clock

(to end the wait insertion)

[5]

Wait for 1 byte to be received.

(9th clock rising edge)

[8]

Wait for the next data to be

received.

(8th clock falling edge)

[6]

Read the receive data.

[13] Set WAIT = 0.

Read ICDR.

Clear IRIC.

(Note: After setting WAIT = 0, IRIC

should be cleared to 0.)

[14] Stop condition issuance.

Master receive operation

Read IRIC in ICCR

IRIC = 1 ?

Yes

[12] Wait for 1 byte to be received.

Figure 16.15 Flowchart for Master Receive Mode (Example)

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