HD64F2149YV datasheet(521/1075 Pages) RENESAS

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 493 of 1044

REJ09B0280-0300

Section 16 I

2C Bus Interface

16.1

Overview

A two-channel I

2C bus interface is available for the H8S/2169 or H8S/2149. The I2C bus interface

conforms to and provides a subset of the Philips I

2C bus (inter-IC bus) interface functions. The

2C bus differs partly from the Philips configuration,

however.

Each I

2C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer

data, saving board and connector space.

16.1.1

Features

• Selection of addressing format or non-addressing format

 I2C bus format: addressing format with acknowledge bit, for master/slave operation

 Serial format: non-addressing format without acknowledge bit, for master operation only

• Conforms to Philips I2C bus interface (I2C bus format)

• Two ways of setting slave address (I2C bus format)

• Start and stop conditions generated automatically in master mode (I2C bus format)

• Selection of acknowledge output levels when receiving (I2C bus format)

• Automatic loading of acknowledge bit when transmitting (I2C bus format)

• Wait function in master mode (I2C bus format)

A wait can be inserted by driving the SCL pin low after data transfer, excluding

acknowledgement. The wait can be cleared by clearing the interrupt flag.

• Wait function in slave mode (I2C bus format)

A wait request can be generated by driving the SCL pin low after data transfer, excluding

acknowledgement. The wait request is cleared when the next transfer becomes possible.

• Three interrupt sources

 Data transfer end (including transmission mode transition with I2C bus format and address

reception after loss of master arbitration)

 Address match: when any slave address matches or the general call address is received in

slave receive mode (I

2C bus format)

 Stop condition detection

• Selection of 16 internal clocks (in master mode)

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