HD64F2149YV datasheet(478/1075 Pages) RENESAS

478 / 1075 page

Section 15 Serial Communication Interface (SCI, IrDA)

Rev. 3.00 Jan 18, 2006 page 450 of 1044

REJ09B0280-0300

15.2.9

Serial Interface Mode Register (SCMR)

—

SDIR

R/W

SMIF

R/W

SINV

R/W

—

Bit

Initial value

Read/Write

SCMR is an 8-bit readable/writable register used to select SCI functions.

SCMR is initialized to H'F2 by a reset, and in standby mode, watch mode, subactive mode,

subsleep mode, and module stop mode.

Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.

Bit 3—Data Transfer Direction (SDIR): Selects the serial/parallel conversion format.

Bit 3

SDIR

Description

TDR contents are transmitted LSB-first

(Initial value)

Receive data is stored in RDR LSB-first

TDR contents are transmitted MSB-first

Receive data is stored in RDR MSB-first

Bit 2—Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not

affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/

E bit in

SMR.

Bit 2

SINV

Description

TDR contents are transmitted without modification

(Initial value)

Receive data is stored in RDR without modification

TDR contents are inverted before being transmitted

Receive data is stored in RDR in inverted form

Bit 1—Reserved: This bit cannot be modified and is always read as 1.

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