HD64F2149YV datasheet(463/1075 Pages) RENESAS

463 / 1075 page

Section 15 Serial Communication Interface (SCI, IrDA)

Rev. 3.00 Jan 18, 2006 page 435 of 1044

REJ09B0280-0300

15.2.6

Serial Control Register (SCR)

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

Read/Write

SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output

in asynchronous mode, and interrupt requests, and selection of the serial clock source.

SCR can be read or written to by the CPU at all times.

SCR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep

mode, and module stop mode.

Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt

(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE

flag in SSR is set to 1.

Bit 7

TIE

Description

Transmit-data-empty interrupt (TXI) request disabled*

(Initial value)

Transmit-data-empty interrupt (TXI) request enabled

Note:

TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,

then clearing it to 0, or clearing the TIE bit to 0.

Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI)

request and receive-error interrupt (ERI) request generation when serial receive data is transferred

from RSR to RDR and the RDRF flag in SSR is set to 1.

Bit 6

RIE

Description

Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request

disabled*

(Initial value)

Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request

enabled

Note:

RXI and ERI interrupt request cancellation can be performed by reading 1 from the

RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.

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