HD64F2149YV datasheet(416/1075 Pages) RENESAS

416 / 1075 page

Section 13 Timer Connection

Rev. 3.00 Jan 18, 2006 page 388 of 1044

REJ09B0280-0300

Bit 5

CLOE

Description

The P64/FTIC/

KIN4/CIN4/CLAMPO pin functions as the P64/FTIC/KIN4/CIN4 pin

(Initial value)

The P64/FTIC/

KIN4/CIN4/CLAMPO pin functions as the CLAMPO pin

Bit 4

CBOE

Description

The P27/A15/PW15/CBLANK pin functions as the P27/A15/PW15 pin

(Initial value)

In mode 1 (expanded mode with on-chip ROM disabled):

The P27/A15/PW15/CBLANK pin functions as the A15 pin

In modes 2 and 3 (modes with on-chip ROM enabled):

The P27/A15/PW15/CBLANK pin functions as the CBLANK pin

Bits 3 to 0—Output Synchronization Signal Inversion (HOINV, VOINV, CLOINV,

CBOINV): These bits select inversion of the output phase of the horizontal synchronization signal

(HSYNCO), the vertical synchronization signal (VSYNCO), the clamp waveform (CLAMPO),

and the blank waveform (CBLANK).

Bit 3

HOINV

Description

The IHO signal is used directly as the HSYNCO output

(Initial value)

The IHO signal is inverted before use as the HSYNCO output

Bit 2

VOINV

Description

The IVO signal is used directly as the VSYNCO output

(Initial value)

The IVO signal is inverted before use as the VSYNCO output

Bit 1

CLOINV

Description

The CLO signal (CL1, CL2, CL3, or CL4 signal) is used directly as the CLAMPO

output

(Initial value)

The CLO signal (CL1, CL2, CL3, or CL4 signal) is inverted before use as the

CLAMPO output

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