HD64F2149YV datasheet(382/1075 Pages) RENESAS

382 / 1075 page

Section 12 8-Bit Timers

Rev. 3.00 Jan 18, 2006 page 354 of 1044

REJ09B0280-0300

Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether the OVF interrupt request

(OVI) is enabled or disabled when the OVF flag in TCSR is set to 1.

Note that an OVI interrupt is not requested by TMRX, regardless of the OVIE value.

Bit 5

OVIE

Description

OVF interrupt request (OVI) is disabled

(Initial value)

OVF interrupt request (OVI) is enabled

Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select the method by which

the timer counter is cleared: by compare-match A or B, or by an external reset input.

Bit 4

Bit 3

CCLR1

CCLR0

Description

Clearing is disabled

(Initial value)

Cleared on compare-match A

Cleared on compare-match B

Cleared on rising edge of external reset input

Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to

TCNT is an internal or external clock.

The input clock can be selected from either six or three clocks, all divided from the system clock

(

φ). The falling edge of the selected internal clock triggers the count.

When use of an external clock is selected, three types of count can be selected: at the rising edge,

the falling edge, and both rising and falling edges.

Some functions differ between channel 0 and channel 1, because of the cascading function.

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