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HD64F2149YV Folha de dados(PDF) 361 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 361 Page - Renesas Technology Corp |
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361 / 1075 page ![]() Section 11 16-Bit Free-Running Timer Rev. 3.00 Jan 18, 2006 page 333 of 1044 REJ09B0280-0300 11.3.5 Timing of Input Capture Flag (ICFA to ICFD) Setting The input capture flag ICFx (x = A to D) is set to 1 by the internal input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRx). Figure 11.11 shows the timing of this operation. ICFA/B/C/D φ FRC Input capture signal N N ICRA/B/C/D Figure 11.11 Setting of Input Capture Flag (ICFA/B/C/D) |
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