HD64F2149YV datasheet(342/1075 Pages) RENESAS

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Section 11 16-Bit Free-Running Timer

Rev. 3.00 Jan 18, 2006 page 314 of 1044

REJ09B0280-0300

11.2.3

Input Capture Registers A to D (ICRA to ICRD)

Bit

Initial

value

Write

Read/

There are four input capture registers, A to D, each of which is a 16-bit read-only register.

When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID) is

detected, the current FRC value is copied to the corresponding input capture register (ICRA to

ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set to

1. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR.

ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, and made to

perform buffer operations, by means of buffer enable bits A and B (BUFEA, BUFEB) in TCR.

Figure 11.2 shows the connections when ICRC is specified as the ICRA buffer register (BUFEA =

1). When ICRC is used as the ICRA buffer, both rising and falling edges can be specified as

transitions of the external input signal by setting IEDGA

≠ IEDGC. When IEDGA = IEDGC,

either the rising or falling edge is designated. See table 11.3.

Note:

The FRC contents are transferred to the input capture register regardless of the value of

the input capture flag (ICF).

BUFEA

IEDGA

IEDGC

FTIA

Edge detect and

capture signal

generating circuit

FRC

ICRC

ICRA

Figure 11.2 Input Capture Buffering (Example)

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