HD64F2149YV datasheet(332/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 10 14-Bit PWM Timer

Rev. 3.00 Jan 18, 2006 page 304 of 1044

REJ09B0280-0300

10.4

Operation

A PWM waveform like the one shown in figure 10.3 is output from the PWMX pin. When OS =

0, the value in DADR corresponds to the total width (T

L) of the low (0) pulses output in one

conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 1, the output

waveform is inverted and the DADR value corresponds to the total width (T

H) of the high (1)

output pulses. Figure 10.4 shows the types of waveform output available.

TL = ∑ tLn (when OS = 0)

n = 1

1 conversion cycle

× 214 (= 16384))

Basic cycle

× 64 or T × 256)

T: Resolution

(When CFS = 0, m = 256; when CFS = 1, m = 64)

Figure 10.3 PWM D/A Operation

Table 10.4 summarizes the relationships of the CKS, CFS, and OS bit settings to the resolution,

base cycle, and conversion cycle. The PWM output remains flat unless DADR contains at least a

certain minimum value. Table 10.4 indicates the range of DADR settings that give an output

waveform like the one in figure 10.3, and lists the conversion cycle length when low-order DADR

bits are kept cleared to 0, reducing the conversion precision to 12 bits or 10 bits.

HD64F2149YV Folha de dados(PDF) 332 Page - Renesas Technology Corp