M32CSLASH8B datasheet(246/406 Pages) RENESAS

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Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 229 of 385

Table 17.10

Functions in I2C Mode (2/2)

i = 0 to 4

NOTES:

1. Set default value of the SDAi output while bits SMD2 to SMD0 in the UiMR register are set to 000b (serial

interface disabled).

2. Second data transfer to the UiRB register (at the rising edge of the ninth bit of SCLi).

3. First data transfer to the UiRB register (at the falling edge of the ninth bit of SCLi).

Function

I2C Mode (SMD2 to SMD0 = 010b, IICM = 1)

IICM2 = 0

(NACK/ACK interrupt)

IICM2 = 1

(UART transmit/receive interrupt)

CKPH = 0

(no clock delay)

CKPH = 1

(clock delay)

CKPH = 0

(no clock delay)

CKPH = 1

(clock delay)

Reading RXDi, SCLi pin

levels

Can be read regardless of the corresponding port direction bit

Default value of TXDi,

SDAi output

Value set in the port register before entering I2C mode(1)

SCLi default and end

values

DMA source

(See Figure 17.24)

Acknowledgement detection (ACKi)

UARTi receive operation - at the falling edge

of 9th bit of SCLi

Storing receive data

1st to 8th bit of the receive data are stored

into bits 7 to 0 in the UiRB register

1st to 7th bits of the receive data are stored

into bits 6 to 0 in the UiRB register. 8th bit is

stored into bit 8 in the UiRB register

1st to 8th bits are

stored into bits 7 to 0

in the UiRB

Reading receive data

The value in the UiRB register is read as it is

Bits 6 to 0 in the UiRB

bits 7 to 1. Bit 8 in the

UiRB register is read

as bit 0(3)

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