M32CSLASH8B datasheet(242/406 Pages) RENESAS

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SDHI

ALS

ACKC

STSPSEL

Delay circuit

D Q

UARTi transmit

shift register

Start condition detection

Stop condition detection

SDAi

Select SDA output

in Function Control

SCLi

Select SCL output in

Function Control

ACKD

Noise

filter

Noise

filter

UARTi

CLK

control

S Q

SWC

SWC2

Falling edge

of 9th bit

Transmission

control circuit

UARTi transmit interrupt request

NACK interrupt request

DMA 0 to 3 request

UARTi transmit

shift register

Start/stop condition detection

interrupt request

S Q

Reception

control circuit

UARTi receive interrupt request

ACK interrupt request

DMA 0 to 3 request

D Q

9th clock

NACK

ACK

Logic 0 write

signal to PDk_m

Logic 1 write

signal to PDk_m

D Q

IICM = 0 or

IICM2 = 1

IICM = 1 and

IICM2 = 0

IICM = 0 or

IICM2 = 1

IICM = 1 and

IICM2 = 0

ABT

BBS

i = 0 to 4

IICM, BBS: bits in the UiSMR register

IICM2, SWC, ALS, SWC2, SDHI: bits in the UiSMR2 register

STSPSEL, ACKD, ACKC: bits in the UiSMR4 register

NCH: bit in the UiC0 register

ABT: UiRB register

PDk_m: bit in the Port Pk Direction Register corresponding to the SCLi pin

NOTES:

1. P7_0 and P7_1 do not have the dotted rectangular portion of the circuit. The absolute maximum rating of the input voltage for P7_0 and P7_1 is

from -0.3 V to 6.0 V.

2. P6_2, P6_3, P6_6, P6_7, P9_1, P9_2, P9_6, and P9_7 are used with turning off the P channel of the CMOS port all the time. The absolute

maximum rating of the input voltage for these ports is from - 0.3 V to VCC1 + 0.3 V.

STSPSEL IICM

Start/stop condition

generation block

Falling edge

detection

NCH

(note 1, 2)

Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 225 of 385

Figure 17.23

I2C Mode Block Diagram

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