M32CSLASH8B datasheet(243/406 Pages) RENESAS

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Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 226 of 385

Table 17.7

i = 0 to 4

Bit

Setting Value

Master

Slave

UiMR

SMD2 to SMD0

Set to 010b

CKDIR

Set to 0

Set to 1

IOPOL

Set to 0

UiSMR

IICM

Set to 1

ABC

Select an arbitration lost detect timing Disabled

BBS

Bus busy flag

7 to 3

Set to 00000b

UiSMR2

IICM2

See Tables 17.9 and 17.10 Functions in I2C Mode

CSC

Set to 1 to enable clock

synchronization

Set to 0

SWC

Set to 1 to hold an “L” signal output from SCLi at the falling edge of the ninth

bit of the serial clock

ALS

Set to 1 to abort an SDAi output when

detecting the arbitration lost

Set to 0

STC

Set to 0

Set to 1 to initialize UARTi by

detecting the start condition

SWC2

Set to 1 to forcibly make a signal output from SCL an “L”

SDHI

Set to 1 to disable SDA output

SU1HIM

Set to 0

UiSMR3

SSE

Set to 0

CKPH

See Tables 17.9 and 17.10 Functions in I2C Mode

DINC, NODC, ERR

Set to 0

DL2 to DL0

Set SDAi digital delay value

UiSMR4

STAREQ

Set to 1 to generate the start

condition

Set to 0

RSTAREQ

Set to 1 to generate the restart

condition

STPREQ

Set to 1 to generate the stop

condition

STSPSEL

Set to 1 when using a condition

generation function

ACKD

Select ACK or NACK

ACKC

Set to 1 to output ACK data

SCLHI

Set to 1 to enable SCL output stop

when detecting the stop condition

Set to 0

SWC9

Set to 0

Set to 1 to hold an “L” signal output

from SCLi at the falling edge of the

ninth bit of the serial clock

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