M32CSLASH8B datasheet(245/406 Pages) RENESAS

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Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 228 of 385

As shown in Tables 17.9 and 17.10, I2C mode is entered when bits SMD2 to SMD0 in the UiMR register are set

to 010b (I2C mode) and the IICM bit in the UiSMR register to 1 (I2C mode). Because an SDAi transmit output

passes through a delay circuit, output signal from the SDAi pin changes after the SCLi pin level becomes low

(“L”) and the “L” output stabilizes.

Table 17.9

Functions in I2C Mode (1/2)

i = 0 to 4

NOTE:

Use the following procedures to change an interrupt source.

(a) Disable an interrupt of the corresponding interrupt number.

(b) Change an interrupt source.

(d) Set bits ILVL2 to ILVL0 of the corresponding interrupt number.

Function

I2C Mode (SMD2 to SMD0 = 010b, IICM = 1)

IICM2 = 0

(NACK/ACK interrupt)

IICM2 = 1

(UART transmit/receive interrupt)

CKPH = 0

(no clock delay)

CKPH = 1

(clock delay)

CKPH = 0

(no clock delay)

CKPH = 1

(clock delay)

Interrupt source for

numbers 39 to 41(1)

(See Figure 17.24)

Start condition or stop condition detection

(See Table 17.12 STSPSEL Bit Function)

Interrupt source for

numbers 17, 19, 33, 35,

37(1)

(See Figure 17.24)

No acknowledgement detection (NACKi) -

at the rising edge of 9th bit of SCLi

UARTi transmit

operation - at the

rising edge of 9th bit

of SCLi

UARTi transmit

operation - at the

next falling edge after

the 9th bit of SCLi

Interrupt source for

numbers 18, 20, 34, 36,

38(1)

(See Figure 17.24)

Acknowledgement detection (ACKi) -

at the rising edge of 9th bit of SCLi

UARTi receive operation - at the falling edge

of 9th bit of SCLi

Data transfer timing

from the UART receive

shift register to the UiRB

At rising edge of 9th bit of SCLi

Falling edge of 9th bit

of SCLi

Falling edge and

rising edge of 9th bit

of SCLi

UARTi transmit output

delay

Delay

Functions of P6_3,

P6_7, P7_0, P9_2,

P9_6

SDAi input and output

Functions of P6_2,

P6_6, P7_1, P9_1,

P9_7

SCLi input and output

Noise filter width

200 ns

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