SSM2604CPZ-R2 datasheet(13/28 Pages) AD

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SSM2604

Rev. 0 | Page 13 of 28

es.

audio frame clock signal that separates left- and right-channel

data on the PBDAT lines.

The BCLK signal acts as the digital audio clock. Depending on

if the SSM2604 is in master or slave mode, the BCLK signal is

either an input or an output signal. During a playback opera-

tion, PBDAT and PBLRC must be synchronous to the BCLK

signal to avoid data corruption.

Digital Audio Data Sampling Rate

To accommodate a wide variety of commonly used DAC and

ADC sampling rates, the SSM2604 allows for two modes of

operation, normal and USB, selected by the USB bit (Register R8,

Bit D0).

In normal mode, the SSM2604 supports digital audio sampling

rates from 8 kHz to 96 kHz. Normal mode supports 256 fS and

384 fS based clocks. To select the desired sampling rate, the user

must set the appropriate sampling rate register in the SR control

bits (Register R8, Bit D2 to Bit D5) and match this selection to

the core clock frequency that is pulsed on the MCLK pin.

See Table 25 and Table 26 for guidelin

In USB mode, the SSM2604 supports digital audio sampling

rates from 8 kHz to 96 kHz. USB mode is enabled on the

SSM2604 to support the common universal serial bus (USB)

clock rate of 12 MHz, or to support 24 MHz if the CLKDIV2

control register bit is activated. The user must set the appropriate

sampling rate in the SR control bits (Register R8, Bit D2 to Bit D5).

See Table 25 and Table 26 for guidelines.

Note that the sampling rate is generated as a fixed divider from

the MCLK signal. Because all audio processing references the

core MCLK signal, corruption of this signal, in turn, corrupts

the outgoing audio quality of the SSM2604. The BCLK/RECLRC/

RECDAT or BCLK/PBLRC/PBDAT signals must be synchronized

with MCLK in the digital audio interface circuit. MCLK must

be faster or equal to the BCLK frequency to guarantee that no

data is lost during data synchronization.

The BCLK frequency should be greater than

Sampling Rate × Word Length × 2

Ensuring that the BCLK frequency is greater than this value

guarantees that all valid data bits are captured by the digital

audio interface circuitry. For example, if a 32 kHz digital

audio sampling rate with a 32-bit word length is desired,

BCLK ≥ 2.048 MHz.

RECLRC/

PBLRC

BCLK

RECDAT/

PBDAT

LEFT CHANNEL

RIGHT CHANNEL

X = DON’T CARE.

Figure 19. Left-Justified Audio Input Mode

RECLRC/

PBLRC

BCLK

RECDAT/

PBDAT

LEFT CHANNEL

RIGHT CHANNEL

X = DON’T CARE.

21X

Figure 20. Right-Justified Audio Input Mode

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