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SSM2604CPZ-R2 Folha de dados(PDF) 6 Page - Analog Devices

Nome de Peças SSM2604CPZ-R2
Descrição Electrónicos  Low Power Audio Codec
PDF  28 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

SSM2604CPZ-R2 Folha de dados(HTML) 6 Page - Analog Devices

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SSM2604
Rev. 0 | Page 6 of 28
Table 5. Digital Audio Interface Master Mode Timing
Limit
Parameter
tMIN
tMAX
Unit
Description
tDST
30
ns
PBDAT setup time to BCLK rising edge
tDHT
10
ns
PBDAT hold time to BCLK rising edge
tDL
10
ns
RECLRC/PBLRC propagation delay from BCLK falling edge
tDDA
10
ns
RECDAT propagation delay from BCLK falling edge
tBCLKR
10
ns
BCLK rising time (10 pF load)
tBCLKF
10
ns
BCLK falling time (10 pF load)
tBCLKDS
45:55:00
55:45:00
BCLK duty cycle (normal and USB mode)
BCLK
PBLRC/
RECLRC
PBDAT
RECDAT
tDDA
tDST
tDHT
tDL
Figure 4. Digital Audio Interface Master Mode Timing
Table 6. System Clock Timing
Limit
Parameter
tMIN
tMAX
Unit
Description
tXTIY
72
ns
MCLK/XTI system clock cycle time
tMCLKDS
40:60
60:40:00
MCLK/XTI duty cycle
tXTIH
32
ns
MCLK/XTI system clock pulse width high
tXTIL
32
ns
MCLK/XTI system clock pulse width low
tCOP
20
ns
CLKOUT propagation delay from MCLK/XTI falling edge
tCOPDIV2
20
ns
CLKODIV2 propagation delay from MCLK/XTI falling edge
tCOPDIV2
tCOP
MCLK/XTI
CLKOUT
CLKODIV2
tXTIH
tXTIL
tXTIY
Figure 5. System (MCLK) Clock Timing



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