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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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ST7263B Folha de dados(PDF) 76 Page - STMicroelectronics |
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ST7263B Folha de dados(HTML) 76 Page - STMicroelectronics |
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76 / 132 page  ST7263B 76/132 I²C BUS INTERFACE (Cont’d) The Acknowledge function may be enabled and disabled by software. The I²C interface address and/or general call ad- dress can be selected by software. The speed of the I²C interface may be selected be- tween Standard (0-100 kHz) and Fast I²C (100- 400 kHz). SDA/SCL Line Control Transmitter mode: the interface holds the clock line low before transmission to wait for the micro- controller to write the byte in the Data Register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register. The SCL frequency (FSCL) is controlled by a pro- grammable clock divider which depends on the I²C bus mode. When the I²C cell is enabled, the SDA and SCL ports must be configured as floating open-drain output or floating input. In this case, the value of the external pull-up resistor used depends on the application. When the I²C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins. Figure 40. I²C Interface Block Diagram DATA REGISTER (DR) DATA SHIFT REGISTER COMPARATOR OWN ADDRESS REGISTER (OAR) CLOCK CONTROL REGISTER (CCR) STATUS REGISTER 1 (SR1) CONTROL REGISTER (CR) SDAI SCLI CONTROL LOGIC STATUS REGISTER 2 (SR2) INTERRUPT CLOCK CONTROL DATA CONTROL SCL SDA |
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