Circuit Note

CN-0575

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Rev. 0 | 3 of 7

Figure 4. External ADIN1110 Hybrid

The ADIN1110 has four supply domains that power the different

sections of its internal circuitry, and their connections may vary

based on the requirements of the application. AVDD_H and

AVDD_L can be set to either 3.3 V or 1.8 V depending on

the transmit level mode that needs to be supported, and VDDIO

must be set to the SPI voltage level used by the host processor.

DVDS_1P1 should normally be shorted to the output of the internal

low dropout (LDO) regulator, but can be connected to an external

supply instead for better power efficiency in systems with multiple

ADIN1110 devices.

In CN0575, AVDD_H, AVDD_L and VDDIO are all tied to 3.3 V,

while DVDD_1P1 is connected to the output of the internal LDO

regulator. This configuration eliminates the need to include addition-

al LDO regulators, while at the same time allowing the ADIN1110

PHY to support both 2.4 VP-P and 1.0 VP-P transmit level modes in

the 10BASE-T1L link.

The ADIN1110 requires a 25 MHz reference signal to generate the

different internal clocks needed for its operation. In CN0575, this

signal is produced by a 25 MHz crystal with a tolerance rating of

±10 ppm, a stability rating of ±20 ppm, a maximum ESR of 50 Ω,

a maximum drive level of 100 μW, and a load capacitance rating of

10 pF well within the requirements of the ADIN1110. Refer to the

ADIN1110 data sheet for details.

CONFIGURING THE 10BASE-T1L MAC-PHY

An autonegotiation process is defined in the IEEE 802.3-2022

standard to bring up and link with another 10BASE-T1L device.

This handshaking mechanism enables the ADIN1110 and its link

partner to advertise their Ethernet capabilities, compare them, and

then identify the best operating mode that both devices can sup-

port. For a 10BASE-T1L link, one of the parameters that both PHYs

need to agree on is the transmit level. Typically, a 10BASE-T1L

link uses the standard 1.0 VP-P level; the higher 2.4 VP-P level

can only be used if at least one PHY requests for it and both

devices advertise capability of supporting its operation. By default,

the CN0575 advertises support for both transmit levels.

Autonegotiation also allows the ADIN1110 PHY and its link partner

to establish their controller/peripheral relationship. During this proc-

ess, the two PHYs advertise their preferred modes and compare

them. If their preferences are different, the PHYs are configured

accordingly. Otherwise, the controller and peripheral assignments

will be randomly assigned.

For the ADIN1110, the default advertised controller/peripheral pref-

erence during autonegotiation is determined by the logic level of the

TS_TIMER/MS_SEL pin, which is normally held at logic low by an

internal pull-down resistor.

For most applications, the actual controller/peripheral configuration

of the two devices is unimportant. Similar to how a 2.4 VP-P transmit

level operation is requested, the ADIN1110 PHY can be forced

to use its preferred controller/peripheral by setting the appropriate

bit in the 10BASE-T1L autonegotiation advertisement register, if

needed. In this case, the link partner is configured into the opposite

mode during the autonegotiation process. It should be noted that

if the link partner is set up such that it is forced to use the

same controller/peripheral configuration, then a fault occurs, and

the autonegotiation process fails.

The ADIN1110 PHY can be reconfigured to advertise a different

transmit level capability and controller/peripheral configuration pref-

erence if the default settings do not meet the application require-

ments. To do this, the following procedure should be done prior to

bringing up a link:

►

Place the ADIN1110 into software power-down mode using the

software power-down control register.

►

Access the PHY registers via the MDIO access registers to

produce the desired configuration.

►

Exit software power-down mode to initiate autonegotiation.

The ADIN1110 can also be placed immediately into software pow-

er-down mode after a reset operation by pulling the SWPD_EN

pin high. For added flexibility, the CN0575 allows the user to

select the software power down mode. This provides an easy way

to implement or skip software power-down as needed. For more

details on the ADIN1110 registers, refer to the device data sheet.

Table 1 summarizes how to select the initial operating mode of the

ADIN1110 PHY core using the different mode selection pins. The

CN0575's default configuration maximizes the compatibility with

most controller configurations.

Table 1. ADIN1110 Operating Mode Configuration

ADIN1110 Pin

Logic Level

Operating Mode

TX2P4_EN

High

Only 1.0 VP-P transmit level is supported.

Low

Both 1.0 VP-P and 2.4 VP-P transmit levels are

supported. Default for CN0575.

TS_TIMER/

MS_SEL

High

PHY prefers to be configured as a controller

device.

Low

PHY prefers to be configured as a peripheral

device. Default for CN0575.

SWPD_EN

High

PHY immediately starts autonegotiation after

reset.

Low

PHY enters software power-down mode after

reset. Default for CN0575.