R5F56517FDFM datasheet(98/188 Pages) RENESAS

98 / 188 page

R01DS0276EJ0240 Rev.2.40

Page 98 of 188

Oct 31, 2023

RX65N Group, RX651 Group

2. Electrical Characteristics

2.4

AC Characteristics

Note 1. The FCLK must run at a frequency of at least 4 MHz when changing the flash memory contents.

Note 1. When the 12-bit A/D converter is used, the frequency must be set to at least 1 MHz.

Table 2.11

Operating Frequency (High-Speed Operating Mode)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Operating

frequency

System clock (ICLK)

—

120

MHz

Peripheral module clock (PCLKA)

—

120

Peripheral module clock (PCLKB)

—

Peripheral module clock (PCLKC)

—

Peripheral module clock (PCLKD)

—

Flash-IF clock (FCLK)

—*1

—60

External bus clock (BCLK)

Package of 144 pins or more

—

120

100-pin package

—

BCLK pin output

Package of 144 pins or more

—

100-pin package

—

SDRAM clock (SDCLK)

Package of 144 pins or more

—

SDCLK pin output

Package of 144 pins or more

—

Table 2.12

Operating Frequency (Low-Speed Operating Mode 1)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Operating

frequency

System clock (ICLK)

—

MHz

Peripheral module clock (PCLKA)

—

Peripheral module clock (PCLKB)

—

Peripheral module clock (PCLKC)*1

——

Peripheral module clock (PCLKD)*1

——

Flash-IF clock (FCLK)

—

External bus clock (BCLK)

Package of 144 pins or more

—

100-pin package

—

BCLK pin output

Package of 144 pins or more

—

100-pin package

—

SDRAM clock (SDCLK)

Package of 144 pins or more

—

SDCLK pin output

Package of 144 pins or more

—

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