M50FW016N1T datasheet(15/45 Pages) STMICROELECTRONICS

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M50FW016

Table 6. FWH Bus Write Field Definitions (Quadruple Byte Program)

Figure 7. FWH Bus Write Waveforms (Quadruple Byte Program)

Clock

Cycle

Number

Clock

Cycle

Count

Field

FWH0-

FWH3

Memory

I/O

Description

START

1110b

On the rising edge of CLK with FWH4 Low, the contents of

FWH0-FWH3 indicate the start of a FWH Write Cycle.

IDSEL

XXXX

Indicates which FWH Flash Memory is selected. The value

on FWH0-FWH3 is compared to the IDSEL strapping on the

FWH Flash Memory pins to select which FWH Flash

Memory is being addressed.

3-9

ADDR

XXXX

A 28-bit address phase is transferred starting with the most

significant nibble first. The A1-A0 lines are treated as Don't

Care.

MSIZE

0010b

Always 0010b (quadruple byte transfer).

11-18

DATA

XXXX

Data transfer is two cycles, starting with the least significant

nibble. (The first pair of nibbles is that at the address with A1-

A0 set to 00, the second pair with A1-A0 set to 01, the third

pair with A1-A0 set to 10, and the fourth pair with A1-A0 set

to 11.)

TAR

1111b

The host drives FWH0-FWH3 to 1111b to indicate a

turnaround cycle.

TAR

1111b

(float)

The FWH Flash Memory takes control of FWH0-FWH3

during this cycle.

SYNC

0000b

The FWH Flash Memory drives FWH0-FWH3 to 0000b,

indicating it has received data or a command.

TAR

1111b

The FWH Flash Memory drives FWH0-FWH3 to 1111b,

indicating a turnaround cycle.

TAR

1111b

(float)

N/A

The FWH Flash Memory floats its outputs and the host takes

control of FWH0-FWH3.

AI05784

CLK

FWH4

FWH0-FWH3

Number of

clock cycles

START

IDSEL

ADDR

MSIZE

DATA

TAR

SYNC

TAR

11718212

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