M50FW016N1T datasheet(11/45 Pages) STMICROELECTRONICS

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M50FW016

BUS OPERATIONS

The two interfaces have similar bus operations but

the signals and timings are completely different.

The Firmware Hub (FWH) Interface is the usual

interface and all of the functionality of the part is

available through this interface. Only a subset of

functions are available through the Address/

Address Multiplexed (A/A Mux) Interface.

Follow the section Firmware Hub (FWH) Bus

Operations below and the section Address/

Address Multiplexed (A/A Mux) Bus Operations

below for a description of the bus operations on

each interface.

Firmware Hub (FWH) Bus Operations

The Firmware Hub (FWH) Interface consists of

four data signals (FWH0-FWH3), one control line

(FWH4) and a clock (CLK). In addition protection

against accidental or malicious data corruption

can be achieved using two further signals (TBL

and WP). Finally two reset signals (RP and INIT)

are available to put the memory into a known

state.

The data signals, control signal and clock are

designed to be compatible with PCI electrical

specifications. The interface operates with clock

speeds up to 33MHz.

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Standby, Reset and Block Protection.

Bus Read. Bus Read operations read from the

memory cells, specific registers in the Command

Interface or Firmware Hub Registers. A valid Bus

Read operation starts when Input Communication

Frame, FWH4, is Low, VIL, as Clock rises and the

correct Start cycle is on FWH0-FWH3. On the

following clock cycles the Host will send the

Memory ID Select, Address and other control bits

on FWH0-FWH3. The memory responds by

outputting Sync data until the wait-states have

elapsed followed by Data0-Data3 and Data4-

Data7.

Refer to Table 4., FWH Bus Read Field Defini-

tions, and Figure 5., FWH Bus Read Waveforms

(Single Byte Read), for a description of the Field

definitions for each clock cycle of the transfer. See

Table 23., FWH Interface AC Signal Timing Char-

acteristics and Figure 11., FWH Interface AC Sig-

nal Timing Waveforms, for details on the timings of

the signals.

FWH Bus Write. Bus Write operations write to

the

Command

Interface

Firmware

Hub

Registers. A valid Bus Write operation starts when

Input Communication Frame, FWH4, is Low, VIL,

as Clock rises and the correct Start cycle is on

FWH0-FWH3. On the following Clock cycles the

Host will send the Memory ID Select, Address,

other control bits, Data0-Data3 and Data4-Data7

on FWH0-FWH3. The memory outputs Sync data

until the wait-states have elapsed.

Refer to Table 5., FWH Bus Write Field Definitions

(Single Byte), and Figure 6., FWH Bus Write

Waveforms (Single Byte), for a description of the

Field definitions for each clock cycle of the

transfer. See Table 23., FWH Interface AC Signal

Timing Characteristics, and Figure 11., FWH

Interface AC Signal Timing Waveforms, for details

on the timings of the signals.

Bus Abort. The Bus Abort operation can be used

to immediately abort the current bus operation. A

Bus Abort occurs when FWH4 is driven Low, VIL,

during the bus operation; the memory will tri-state

the Input/Output Communication pins, FWH0-

FWH3.

Note that, during a Bus Write operation, the

Command

Interface

starts

executing

the

command as soon as the data is fully received; a

Bus Abort during the final TAR cycles is not

guaranteed to abort the command; the bus,

however, will be released immediately.

Standby. When FWH4 is High, VIH, the memory

is put into Standby mode where FWH0-FWH3 are

put into a high-impedance state and the Supply

Current is reduced to the Standby level, ICC1.

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high-impedance. The memory is

in Reset mode when Interface Reset, RP, or CPU

Reset, INIT, is Low, VIL. RP or INIT must be held

Low, VIL, for tPLPH. The memory resets to Read

mode upon return from Reset mode and the Lock

Registers return to their default states regardless

of their state before Reset, see Table 13. If RP or

INIT goes Low, VIL, during a Program or Erase

operation, the operation is aborted and the

memory cells affected no longer contain valid

data; the memory can take up to tPLRH to abort a

Program or Erase operation.

Block Protection. Block

Protection

can

forced using the signals Top Block Lock, TBL, and

Write Protect, WP, regardless of the state of the

Lock Registers.

Address/Address Multiplexed (A/A Mux) Bus

Operations

The Address/Address Multiplexed (A/A Mux)

Interface has a more traditional style interface.

The signals consist of a multiplexed address

signals (A0-A10), data signals, (DQ0-DQ7) and

three control signals (RC, G, W). An additional

signal, RP, can be used to reset the memory.

The Address/Address Multiplexed (A/A Mux)

Interface

included

for

use

Flash

Programming

equipment

for

faster

factory

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