S32K310 datasheet(76/164 Pages) NXP

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Table 29. 5.0V (4.5V - 5.5V) GPIO Output AC Specification...continued

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

TR_TF_50_SP

5.0V Standard Plus

GPIO rise/fall time [1]

[2][3][4]

3.4

—

DSE=1 CL (max)

=50pF

—

TR_TF_50_M

5.0V Medium GPIO

rise/fall time [1][2][3]

1.8

—

8.2

DSE=0, SRE=0 CL

(max) = 25pF

—

TR_TF_50_M

5.0V Medium GPIO

rise/fall time [1][2][3]

2.5

—

9.8

DSE=0, SRE=1 CL

(max) = 25pF

—

TR_TF_50_M

5.0V Medium GPIO

rise/fall time [1][2][3]

0.7

—

4.5

DSE=1, SRE=0 CL

(max) = 25pF

—

TR_TF_50_M

5.0V Medium GPIO

rise/fall time [1][2][3]

1.8

—

7.2

DSE=1, SRE=1 CL

(max) = 25pF

—

TR_TF_50_M

5.0V Medium GPIO

rise/fall time [1][2][3][4]

3.95

—

13.2

DSE=0, SRE=0 CL

(max) = 50pF

—

TR_TF_50_M

5.0V Medium GPIO

rise/fall time [1][2][3][4]

4.3

—

13.8

DSE=0, SRE=1 CL

(max) = 50pF

—

TR_TF_50_M

5.0V Medium GPIO

rise/fall time [1][2][3][4]

1.6

—

7.1

DSE=1, SRE=0 CL

(max) = 50pF

—

TR_TF_50_M

5.0V Medium GPIO

rise/fall time [1][2][3][4]

2.7

—

9.6

DSE=1, SRE=1 CL

(max) = 50pF

—

TR_TF_50_F

5.0V Fast GPIO rise/

fall time [1][2][3]

0.4

—

3.15

DSE=0, SRE=0 CL

(max) = 25pF

—

TR_TF_50_F

5.0V Fast GPIO rise/

fall time [1][2][3]

1.5

—

6.7

DSE=0, SRE=1 CL

(max) = 25pF

—

TR_TF_50_F

5.0V Fast GPIO rise/

fall time [1][2][3]

0.3

—

2.02

DSE=1, SRE=0 CL

(max) = 25pF

—

TR_TF_50_F

5.0V Fast GPIO rise/

fall time [1][2][3]

0.9

—

4.85

DSE=1, SRE=1 CL

(max) = 25pF

—

TR_TF_50_F

5.0V Fast GPIO rise/

fall time [1][2][3][4]

1.0

—

5.8

DSE=0, SRE=0 CL

(max) = 50pF

—

TR_TF_50_F

5.0V Fast GPIO rise/

fall time [1][2][3][4]

1.9

—

8.5

DSE=0, SRE=1 CL

(max) = 50pF

—

TR_TF_50_F

5.0V Fast GPIO rise/

fall time [1][2][3][4]

0.9

—

3.0

DSE=1, SRE=0 CL

(max) = 50pF

—

TR_TF_50_F

5.0V Fast GPIO rise/

fall time [1][2][3][4]

1.3

—

6.1

DSE=1, SRE=1 CL

(max) = 50pF

—

[1] GPIO rise/fall time specifications are derived from simulation model for the defined operating points (between 20% and 80% of VDD_HV_A/B level). Actual

application rise/fall time should be extracted from IBIS model simulations with the microcontroller models and application PCB.

[2] GPIO output transistion time information can be obtained from the device IBIS model. IBIS models are recommended for system level simulations, as discrete

values for I/O transition times are not representative of the I/O pad behavior when connected to an actual transmission line load.

[3] I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below. A lumped 8pF load (typical) is

assumed at the end of a 5 inch microstrip trace on standard FR4 with approximately 3.3pF/inch. For best signal integrity, the series resistance in the

transmission line should be matched closely to the selected output resistance (ROUT_*) of the I/O pad.

[4] Output timing valid for maximum external load C L = 50pF (includes PCB trace, package trace, and external device input load).

NXP Semiconductors

S32K3XX

S32K3xx Data Sheet

S32K3XX

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Product data sheet

Rev. 13 — 12 November 2025

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