CY244/45ZXC
Document #: 38-07748 Rev. **
Page 5 of 9
Test and Measurement Set-up
Voltage and Timing Definitions
Note:
6. Excluding any output configured as a reference.
7. Jitter measurement will vary. Actually jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, and device programming.
AC Parameters
Parameter[4]
Description
Conditions
Min. Typ. Max. Units
1/t1
Output Frequency
PLL minmax/Dividermaximum
4.2
–
166
MHz
DC1[6]
Output Duty Cycle
Duty Cycle is defined in Figure 3; t2/t1, 50% of VDD
External reference duty cycle between 40% and 60% measured at
VDD/2 (Clock output is ≤ 125MHz)
45
50
55
%
DC2
Output Duty Cycle
Duty Cycle is defined in Figure 3; t2/t1, 50% of VDD
External reference duty cycle between 40% and 60% measured at
VDD/2 (Clock output is > 125MHz)
40
50
60
%
DCREFOUT
Reference Output Duty
Cycle
Duty Cycle is defined in Figure 3; t2/t1, 50% of VDD
(XIN Duty Cycle = 45/55%)
40
50
60
%
ER
Rising Edge Rate
Output Clock Edge Rate. Measured from 20% to 80% of
VDD. CLOAD = 15 pF. See Figure 4.
0.8
1.2
–
V/ns
EF
Falling Edge Rate
Output Clock Edge Rate. Measured from 80% to 20% of
VDD. CLOAD = 15pF See Figure 4.
0.8
1.2
–
V/ns
T9[7]
Clock Jitter
Period Jitter
–
±250
–
ps
T10
PLL Lock Time
–1
5
ms
f∆XO
VCXO Crystal Pull
Range
Using Crystal specified in “Pullable Crystal Specifications” table.
Nominal Crystal Frequency Input assumed (0ppm)@25°C and 3.3V
±120
–
–
ppm
DUT
V
DDs
Outputs
C
LOAD
GND
0.1
µF
t
2
t
1
Clock
Output
0V
V
DD
50% of V
DD
Figure 3. Duty Cycle Definition
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