ADAR4002ACPZ-R7 datasheet(8/66 Pages) AD

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Data Sheet

ADAR4002

SPECIFICATIONS

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TIMING SPECIFICATIONS

V1P2 = 1.2 V, V1P0 = 1.0 V, and TA = 25°C, unless otherwise noted. See Figure 3, Figure 4, Figure 5, and Figure 8 for the supporting timing

figures.

Table 2. SPI Timing

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Maximum Clock Rate (1/tCLK_IN)

100

MHz

Minimum Clock Period (tCLK_IN)

Minimum Pulse Width High (tPWH)1

Minimum Pulse Width Low (tPWL)1

Minimum Setup Time, DATA_IO to CLK_IN (tDS)

2.5

Minimum Hold Time, DATA_IO to CLK_IN (tDH)

Data Valid, CLK_IN to DATA_O (tDV)

Setup Time, CSB_CLKO to CLK_IN (tDCS)

DATA_IO and DATA_O Rise Time (tR)

Outputs loaded with 80 pF, 10% to 90%

Minimum Clock to Update (tCLK_IN-UPDATE)

Minimum CSB_CLKO to Update (tCSB_CLKO-UPDATE)

Minimum Update to Update (tUPDATE-UPDATE)

Minimum Update Pulse width (tUPW)

RF Settling Time (tRF_SETTLE)

TDU settling time between TDU code = 0 to TDU code = 127

1 Clock Period = Pulse Width High + Pulse Width Low; however, Minimum Clock Period cannot equal Minimum Pulse Width High + Minimum Pulse Width Low, which allows

for the SPI signals that are not 50% duty cycle. The extreme example is if the pulse width high = 4 ns, then the pulse width low = 6 ns, or vice versa.

Table 3. Shift Register Mode Timing

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Maximum Clock Rate (1/tCLK_IN)

100

MHz

Minimum Clock Period (tCLK_IN)

Minimum Pulse Width High (tPWH)1

Minimum Pulse Width Low (tPWL)1

Minimum Setup Time, DATA_IO to CLK_IN (tDS)

2.5

Minimum Hold Time, DATA_IO to CLK_IN (tDH)

Data Valid, CLK_IN to DATA_O (tDV)

DATA_IO, DATA_O Rise Time (tR)

Outputs loaded with 80 pF, 10% to 90%

Minimum Clock to Update (tCLK_IN-UPDATE)

RF Settling Time (tRF_SETTLE)

TDU settling time between TDU code = 0 to TDU code = 127

1 Clock Period = Pulse Width High + Pulse Width Low; however, Minimum Clock Period cannot equal Minimum Pulse Width High + Minimum Pulse Width Low, which allows

for the SPI signals that are not 50% duty cycle. The extreme example is if the pulse width high = 4 ns, then the pulse width low = 6 ns, or vice versa.

TIMING DIAGRAMS

Figure 2. SPI Register Timing (MSB First)

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